1. Field of Invention
The present invention relates to a wafer level package. More particularly, the present invention relates to a wafer level package having a button type of contact for engaging with a carrier.
2. Description of Related Art
Following the recent discovery of innovative fabricating techniques in the semiconductor industry, electronic devices are used in a host of electronic products. In general, the manufacturing of semiconductors can be divided into three main stages. In the first stage, a semiconductor substrate is formed. In other words, a single-crystal silicon wafer is grown using epitaxial growth techniques. Next, semiconductor devices such as MOS transistors with all the necessary metallic interconnects for linking various devices are formed. Finally, the silicon chips within the silicon wafer are cut out and then packaged. At present, the design of nearly all packages is aimed towards lighter weight, smaller thickness and installation convenience. Hence, the trend in semiconductor manufacturing is towards an increase in the level of integration, whereas the trend in packaging is to reduce package volume as much as possible. Therefore, packaging techniques such as chip scale package (CSP), multi-chip module (MCM) and chip level package (CLP) have been developed. Because the manufacturing of devices having a line width smaller than 0.18 .mu.m is now possible, the level of integration has increased tremendously. At present, chip manufacturers are looking for packaging methods that can package a silicon chip into the smallest volume. Therefore, packages having a three-dimensional stack-up structure are now being developed. By stacking silicon chips up or stacking silicon chip packages up, overall volume of the ultimate package can be greatly reduced.
FIG. 1 is a cross-sectional view showing the stack-up structure of several integrated circuit packages according to a conventional three-dimensional package. Silicon chips 110a, 110b and 110c are respectively wire-bonded to their lead frames 114a, 114b and 114c. Next, the silicon chips and portions of the lead frames are enclosed by molding material 116, for example, epoxy to form individual silicon chip packages 118a, 118b and 118c respectively. Utilizing the different degree of bending of the outer leads at the outer portions of various lead frames 114a, 114b and 114c, chip packages 118a, 118b and 118c are stacked on top of each other three-dimensionally. The outer leads of the chip package 118c, which lies at the bottom of the stack, are connected to the contact points of a printed circuit board 120. This type of packaging technique is most frequently employed in tape automatic boding (TAB) package.
Although the conventional stack-up type package structure is capable of reducing volume occupation of the final package, suitable carriers (lead frame) have be used to support various silicon chips in addition to the individual or group molding operations required. Hence, not only will the thickness of individual chip packages be increased, the overall thickness of the final stacked type package will be increased as well. Furthermore, since signals to or from the conventional stacked type package must go through a longer conductive path that includes conductive wires and leads, impedance will be increased. Therefore, signal decay and signal delay will increase.
In addition, as soon as the fabrication of the integrated circuit on a semiconductor substrate is complete, a multiple of testing operations has to be carried out such as a probing test, a final test and a burn-in test. Moreover, packaging operations such as wire bonding, molding, lead forming and assembly tests must be conducted once these tests are finished. These operations not only complicate the manufacturing process, but the cost of production will increase as well.
In light of the foregoing, there is a need to provide a simpler chip packaging structure that can eliminate most of the aforementioned processing complications.